ESP32-WROVER is fundamentally broken (but is being fixed by Espressif now)

Update 01/29/2019: Espressif confirmed they are working on a fix in a comment to the GitHub issue today.

Update 02/20/2019: Because this issue is not resolved yet, current versions of low.js for ESP32 only use one core, as this problem does not arise then. This usually does not slow down the JavaScript program, because JavaScript does not run multi-threaded anyways. Thus, low.js/neonious one is stable.

A month ago we reported that PSRAM cache issues still exist with the ESP32, which result into random crashes when using the external RAM of the ESP32-WROVER. These issues exist with the up-to-date revision 1 of the chip.

We noticed these crashes while developing and using low.js. Random crashes/reboots every few hours is definitely something which Espressif should fix quickly.

To help, we created a small sample project, uploaded it to GitHub at ( and opened a GitHub issue with ESP-IDF at However, nothing happened yet.

Today we reevaluated the problem. We made the sample project smaller and learner, tried to understand the problem more and figure out workarounds.

The problem

Writing and then reading in the lower and upper 2 MB of PSRAM at the same time can result into reading old values and not the newly written values, which results into crashes. (This happens in the standard low/high mode, in even/odd mode this happens more randomly). Update: This only happens in Dual-Core mode!

In our sample project this happens when the write is done in a different function than the read. If both are done in the same function, the problem does not exist.


  • Adding asm(“memw”); at the end of each function which stores data to PSRAM seems to work. However, this is slow. BTW: Just adding a few asm(“nop”) does not fix this problem at all
  • Only use the lower 2 MB of PSRAM

We do not like any of the two workarounds. Does anybody have an idea where to continue here?

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2 Replies to “ESP32-WROVER is fundamentally broken (but is being fixed by Espressif now)”

  1. I think I know what is the reason for the random readings (probably writes too) of RAM failure. I am not an electronics engineer, but in my adventure with microcontrollers I have already encountered hardware problems, namely the SPI bus. The transmission between the memory chip and the microcontroller is not checked by the checksum, the communication may be exposed to EMC EMF interference etc. … pins occurring during transmission may cause erroneous data. And the disturbances can generate even ordinary lamp switches … may or may not 🙂 it depends on what electrical installation we have …
    I would like to know what you think about my theory. I’m Polish and unfortunately I wrote through a translator. greetings

    1. Good idea, but most probably not the problem, as exactly the first 2 MB work with the one CPU, the second 2 MB work with the second CPU. Also, switching to single CPU mode fixes the problem. Seems like a ESP32 internal problem to me.

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